| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a hold error correction method and the like for complicated large scale integration in a semiconductor. Ž<P>SOLUTION: Based on timing analyses (S201, S202), hold error path start point information including a set of a hold error amount at a start point and a minimum value in set-up margins for all data paths starting from the start point, and hold error path end point information including a set of a hold error amount at an end point and a minimum value in set-up margins for all data paths reaching the end point, in association with a failed hold error path, are obtained (S203). The hold error path is classified based on whether the hold error is correctable according to the obtained information (S205). The correctable hold error path is grouped based on a certain criterion (S206). Finally, which of the start point and the end point a delay buffer is inserted into is determined per group (S207). Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
