| 摘要 |
A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL−1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.
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