发明名称 |
MULTI-PROTOCOL CHANNEL-AGGREGATED CONFIGURABLE TRANSCEIVER IN AN INTEGRATED CIRCUIT |
摘要 |
Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer ("PCS") circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer ("PMA") circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent ("PMD") sub-layer circuitry. |
申请公布号 |
WO2010045081(A3) |
申请公布日期 |
2010.07.22 |
申请号 |
WO2009US59874 |
申请日期 |
2009.10.07 |
申请人 |
ALTERA CORPORATION;VIJAYARAGHAVAN, DIVYA;WORTMAN, CURT;LEE, CHONG, H. |
发明人 |
VIJAYARAGHAVAN, DIVYA;WORTMAN, CURT;LEE, CHONG, H. |
分类号 |
H04B1/40 |
主分类号 |
H04B1/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|