发明名称 Caching method for NAND flash translation layer
摘要 A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.
申请公布号 US7761648(B2) 申请公布日期 2010.07.20
申请号 US20070844032 申请日期 2007.08.23
申请人 GENESYS LOGIC, INC. 发明人 WU CHIN-HSIEN;KUO TEI-WEI;HSIEH HSIANG-CHI
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
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