发明名称 Techniques for testing memory circuits
摘要 An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
申请公布号 US7761754(B1) 申请公布日期 2010.07.20
申请号 US20080055099 申请日期 2008.03.25
申请人 ALTERA CORPORATION 发明人 ANG CHIN HAI;TAN TZE SIN;ISMAIL ALA-UDDIN;YEOH SIEW LING
分类号 G11C29/00 主分类号 G11C29/00
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