发明名称 |
Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions |
摘要 |
An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.
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申请公布号 |
US7761827(B1) |
申请公布日期 |
2010.07.20 |
申请号 |
US20070832425 |
申请日期 |
2007.08.01 |
申请人 |
CALYPTO DESIGN SYSTEMS, INC. |
发明人 |
RAMACHANDRAN VENKY;TRIPATHI NIKHIL;MATHUR ANMOL;ROY SUMIT;HALDAR MALAY |
分类号 |
G06F17/50;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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