发明名称 Method of reducing a critical dimension of a semiconductor device
摘要 The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.
申请公布号 US7759239(B1) 申请公布日期 2010.07.20
申请号 US20090435552 申请日期 2009.05.05
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 LIN YU CHAO;CHEN DE-FANG;CHANG CHIA-WEI;LIN YIH-ANN;CHEN CHAO-CHENG;CHEN RYAN CHIA-JEN;CHENG WENG
分类号 H01L21/3205 主分类号 H01L21/3205
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