发明名称 CLOCK CIRCUIT WITH CLOCK TRANSFER CAPABILITY AND METHOD
摘要 An apparatus (10) including a multiplexer (20) configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module (22) configured to calculate a phase difference between the source clock and the destination clock and a clock generation module (12) configured to generate a plurality of clocks. The apparatus further includes a clock selection module (14) configured to select one of the plurality of clocks as the transition clock and a control circuit (16) configured to provide: a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.
申请公布号 KR20100082834(A) 申请公布日期 2010.07.20
申请号 KR20107007532 申请日期 2008.09.16
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 BOMMAREDDY SRINIVASA R.;PADMANABHAN UDAY;SONI SAMIR J.;NOMURA KOICHI E.;JUNGELS NICHOLAS F.;BHAN VIVEK
分类号 H03K5/1252;H03K5/01 主分类号 H03K5/1252
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