| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device for decreasing a load applied to a CPU included in the device itself as much as possible during data transfer. Ž<P>SOLUTION: A NAND controller 3 outputs an end notification directly to an ATA I/F controller 1 at each writing of unit-sized data into a RAM 2. At each reception of the end notification, the ATA I/F controller 1 reads the data from the RAM 2 according to descriptors which are created by a CPU 4 and in which the addresses of the data in the RAM 2 are specified in order of transfer, and then transfers the data to a host device 200. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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