| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory cell array which is advantageous to miniturization and is easy to design and manufacture. SOLUTION: A first bit line BL1 connected to a selected memory cell 100 is connected to a ground G, a word line WL connected to the memory cell 100 is specified, a writing voltage is supplied to a second bit line BL2, and data is written in the memory cell 100. The first bit line BL1 connected to the selected memory cell 100 is connected to a sense amplifier, the word line WL connected to the memory cell 100 is specified, a reading voltage is supplied to the second bit line BL2, and data is read out from the memory cell 100. In writing and reading, a voltage of the word line WL is set to a gate threshold voltage of the MOS transistor 110 or higher and a sum of a drive voltage of a circuit for specifying the first bit line BL1 and a gate threshold voltage or lower to specify the word line WL. COPYRIGHT: (C)2010,JPO&INPIT |
