| 摘要 |
<p>An adaptive switch circuit (100) is provided, which includes a CMOS switch (110), an off- level voltage generator (130), and a booster circuit (120). The CMOS switch (110) includes first PMOS (111) and NMOS (112) coupled transistors. The generator provides, via first (103) and second (104) outputs, first and second voltage levels, and includes second PMOS (131) and NMOS (132) transistors. The second PMOS transistor (131) is series connected between VDD and a first bias source (133) and the second NMOS transistor (132) is series connected between VSS and a second bias source (134). The booster circuit (120), which is coupled to the generator (130) between its outputs (103, 104), and to the PMOS (111) and NMOS (112) gates of the CMOS switch, capacitively stores during off level first and second boost voltages (nodes P, N in block 120), which are coupled to the PMOS (111) and NMOS (112) gates. The boost voltages (P, N in block 120) are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.</p> |
