A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
申请公布号
WO2010080342(A2)
申请公布日期
2010.07.15
申请号
WO2009US67663
申请日期
2009.12.11
申请人
FULCRUM MICROSYSTEMS, INC.;DAMA, JONATHAN;LINES, ANDREW