| 摘要 |
PROBLEM TO BE SOLVED: To provide a process and a configuration related to a vertical MOSFET device and a capacitor. SOLUTION: A semiconductor device includes a first layer of a semiconductor material and a field-effect transistor having a first source/drain region formed in the first layer. A channel region is formed over the first layer, and a second source/drain region 235 is formed over the channel region. An integrated circuit structure further includes a capacitor having a bottom plate 266, a dielectric layer 258 and a top capacitor plate 259. In the fabrication method, a first device region selected from a group composed of a source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region 265 is formed on the first device region. The top and the bottom layers with the dielectric layer disposed therebetween are also formed on the semiconductor layer. In another embodiment, the capacitor layer is formed in a trench or window formed in the semiconductor layer. COPYRIGHT: (C)2010,JPO&INPIT |
