发明名称 PLL apparatus
摘要 Provided is a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble For solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.
申请公布号 US7755436(B2) 申请公布日期 2010.07.13
申请号 US20070225565 申请日期 2007.03.30
申请人 NIHON DEMPA KOGYO CO., LTD. 发明人 ONISHI NAOKI;WAKAMATSU SHUNICHI;SHIOBARA TSUYOSHI
分类号 H03L7/08;H03L7/14 主分类号 H03L7/08
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