发明名称 Methods for fabricating low contact resistance CMOS circuits
摘要 Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS transistor and a PMOS transistor disposed in and on a silicon-comprising substrate includes depositing a first silicide-forming metal on the NMOS and PMOS transistors. The first silicide-forming metal forms a silicide at a first temperature. At least a portion of the first silicide-forming metal is removed from the NMOS or PMOS transistor and a second silicide-forming metal is deposited. The second silicide-forming metal forms a silicide at a second temperature that is different from the first temperature. The first silicide-forming metal and the second silicide-forming metal are heated at a temperature that is no less than the higher of the first temperature and the second temperature.
申请公布号 US7754554(B2) 申请公布日期 2010.07.13
申请号 US20070669401 申请日期 2007.01.31
申请人 GLOBALFOUNDRIES INC. 发明人 PEIDOUS IGOR;PRESS PATRICK;BESSER PAUL R.
分类号 H01L21/8238 主分类号 H01L21/8238
代理机构 代理人
主权项
地址
您可能感兴趣的专利