发明名称 |
System and method for bit-reversing and scrambling payload bytes in an asynchronous transfer mode cell |
摘要 |
A method and apparatus are disclosed for efficiently bit-reversing and scrambling one or more bytes of payload data according to DSL standards on a processor. In one embodiment, this is achieved by providing an instruction for bit reversing and scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to bit reverse and scramble data with a single instruction thus allowing for more efficient and faster scrambling operations for subsequent modulation and transmission.
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申请公布号 |
US7756273(B2) |
申请公布日期 |
2010.07.13 |
申请号 |
US20040946305 |
申请日期 |
2004.09.22 |
申请人 |
BROADCOM CORPORATION |
发明人 |
TAUNTON MARK;DOBSON TIMOTHY MARTIN |
分类号 |
H04K1/00;H04L12/28;H04L12/56;H04L12/64 |
主分类号 |
H04K1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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