| 摘要 |
A steady state frequency control circuit for a variable frequency regulator including an open loop frequency control circuit, a frequency detector and a comparator circuit. The variable frequency regulator provides a clock signal indicating actual operating frequency and has a frequency control parameter for adjusting steady state operating frequency. The frequency detector receives the clock signal and provides a frequency sense signal which is compared with a steady state frequency reference signal to provide a frequency adjust signal. The frequency control parameter is adjusted by the frequency adjust signal to control steady state frequency. A method of controlling steady state frequency of a variable frequency regulator includes using open loop frequency control, determining the operating frequency and providing a frequency sense signal, comparing the frequency sense signal with frequency reference signal and providing a frequency adjust signal, and adjusting the frequency control parameter based on the frequency adjust signal.
|
