Sleep control signal sequence circuit

摘要

A sequence circuit includes a switch circuit (30) and a control circuit (50). The switch circuit has an input terminal connected with a node (11) and an output terminal connected to a super I/O chip (10). The control circuit includes a first transistor (Q4) and a second transistor (Q5), the first transistor has a gate connected to the node and a drain connected to a sleep control signal terminal (S3′), the second transistor has a base connected to the drain of the first transistor and a collector connected to the super I/O chip. When the computer is off or in one of the sleep states, the node is at low level and the output terminal of the switch circuit outputs a low level signal; when the computer is on, the node is at high level and the output terminal outputs a high level signal.