发明名称 Method and apparatus for optimizing line writes in cache coherent systems
摘要 A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.
申请公布号 US7757046(B2) 申请公布日期 2010.07.13
申请号 US20020262363 申请日期 2002.09.30
申请人 INTEL CORPORATION 发明人 JAMIL SUJAT;NGUYEN HANG T.;EDIRISOORIYA SAMANTHA J.;MINER DAVID E.;O'BLENESS R. FRANK;TU STEVEN J.
分类号 G06F12/12;G06F12/08 主分类号 G06F12/12
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