AN ASIP ARCHITECTURE FOR DECODING AT LEAST TWO DECODING METHODS

摘要

PURPOSE: An ASIP(Application Specific Instruction set Processor) architecture is provided to satisfy the process amount of 100Mbps when significant area benefits are offered. CONSTITUTION: An ASIP core(101) has a command set including a calculation operator except for multiplication, division, and power. A first memory unit(102) stores data. A transmitting unit transmits data from the first memory unit to the ASIP core. A transmission method comprises a data shuffler(103). A controller independently controls the data shuffler with the ASIP core.