发明名称 PEAK POWER SUPPRESSION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a peak power suppression circuit capable of executing a peak power suppression process of a transmission signal in a transmitter including a multi-antenna system with a small circuit scale. Ž<P>SOLUTION: This peak power suppression circuit 10 includes a channel selection part 12 for accepting a plurality of input signals respectively corresponding to a plurality of antenna channels in a multi-antenna system, and selecting any one of the input signals within the plurality of input signals, executes a peak power suppression process of suppressing peak power generated in the input signal for the one input signal selected by the channel selection part 12, and outputs an output signal corresponding to the one input signal having been subjected to the peak power suppression process along with other output signals. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010154044(A) 申请公布日期 2010.07.08
申请号 JP20080327928 申请日期 2008.12.24
申请人 SUMITOMO ELECTRIC IND LTD 发明人 YAMAMOTO TAKASHI
分类号 H04J11/00;H04B7/06;H04B7/10 主分类号 H04J11/00
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