发明名称 BUFFER DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a buffer device, capable of reducing the waiting time of CPU even when a plurality of block transfer requests is received. Ž<P>SOLUTION: In the buffer device, it is collated whether a read access object area of a read request overlaps with an access object area of each access request stored in an access request storage part 10, and when the read access object area overlaps with the wright access object area of a write request, write data possessed by the write request is acquired from the access request storage part 10 and returned as read data to a CPU 2. When the read access object area overlaps with the transfer source area of a DMA transfer request, the read request is issued to an arbitration circuit part 12 ahead of this DMA transfer request. When the read access object area overlaps with the transfer destination area of the DMA transfer request, the read access object area of the read request is address-converted to the transfer source area of the DMA transfer request, and the resulting read request is issued to the arbitration circuit part 12. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010152837(A) 申请公布日期 2010.07.08
申请号 JP20080332898 申请日期 2008.12.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 TAKEYAMA HARUHIKO
分类号 G06F13/28;G06F13/38 主分类号 G06F13/28
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