发明名称 SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE
摘要 An apparatus for measuring time interval between two selected edges of a clock signal includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.
申请公布号 US2010171529(A1) 申请公布日期 2010.07.08
申请号 US20090498164 申请日期 2009.07.06
申请人 STMICROELECTRONICS PVT. LTD. 发明人 CHATTERJEE KALLOL;TIWARI ANURAG
分类号 G01R29/02 主分类号 G01R29/02
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