| 摘要 |
PURPOSE: A circuit for a delay locked loop is provided to verify the state of a normal operation by continuously comparing the edges of an input clock and a delayed feedback clock. CONSTITUTION: A harmonic lock detector(300) continuously generates up signal or down signal by detecting the generation of abnormal states. The harmonic lock detector includes an up signal generator(310) and a down signal generator. The up signal generator includes a flip-flop unit and a first logical operation unit. The down signal generator includes a part of flip-flops, inverters, NAND-gates, and NOR gates. |
