| 摘要 |
PURPOSE: An analog delay locked loop circuit is provided to precisely control delay cells using a coarse control voltage and a fine control voltage which are generated from a dual charge pump. CONSTITUTION: A voltage control delay unit(100) generates a plurality of clock signals by delaying input clock signals with different time based on a coarse control voltage and a fine control voltage. A phase/frequency detection unit(200) generates up and down pulses which correspond to the detected frequency and phase differences by detecting the frequency and phase differences of output clock signals and the input clock signals. A first charge pump(302) outputs first signal with a pumped level in response to the up and down pulses. A second charge pump(304) generates second signal with a pumped level in response to the up and down pulses. A loop filter(400) generates the coarse control voltage and the fine control voltage. |
