发明名称
摘要 The frequency of a local clock (30) of a local data processor 4 is synchronised to the frequency of a reference clock (10) of a source data processor (2). Both processors (2 and 4) are coupled to a coupled to an asynchronous switched network (6). The method of synchronising comprises sending, to the local data processor (4) from the source data processor (2), timing packets each including at least the destination address of the local processor and a field containing reference clock data indicating the time the packet was launched onto the network and controlling the frequency of the local clock (30) in dependence on the reference clock data. <IMAGE>
申请公布号 JP4497821(B2) 申请公布日期 2010.07.07
申请号 JP20030046444 申请日期 2003.02.24
申请人 发明人
分类号 H04L7/10;H04J3/06;H04N21/242;H04N21/43 主分类号 H04L7/10
代理机构 代理人
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