| 摘要 |
A clock selection circuit and synthesizer that is capable of selecting an optimum clock signal from among a plurality of clock signals in a short time. A reference-clock counter counts clock pulses in an inputted reference clock signal (REF). A clock counter counts clock pulses in one of the plurality of clock signals which is selected by a selection unit and frequency-divided by a frequency divider. An instruction-signal output unit outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit compares the count of the reference-clock counter and the count of the clock counter. The selection unit selects a clock signal by a binary search according to the result of the comparison.
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