发明名称 CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETS
摘要 A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.
申请公布号 US7749830(B2) 申请公布日期 2010.07.06
申请号 US20080026793 申请日期 2008.02.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DORIS BRUCE BENNETT;HENSON WILLIAM K.;WISE RICHARD STEPHEN;YAN HONGWEN
分类号 H01L21/8238 主分类号 H01L21/8238
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