Circuits, architectures, apparatuses, systems, and methods for low voltage clock delay generation

摘要

Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.