发明名称 |
Delay locked loop circuit |
摘要 |
A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.
|
申请公布号 |
US7750699(B2) |
申请公布日期 |
2010.07.06 |
申请号 |
US20080010964 |
申请日期 |
2008.01.31 |
申请人 |
HYNIX SEMICONDUCTOR, INC. |
发明人 |
CHOI HOON |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|