LOW ADDRESS LATCH CIRCUIT FOR SEMICONDUCTOR MEMORY

摘要

PURPOSE: A low address latch circuit for a semiconductor memory is provided to reduce word line enable time in an active mode by removing gate logic in a word line enable route. CONSTITUTION: A low area control unit(10) mixes a test mode signal. The low area control unit generates an initial signal. An initial signal generates a decoder enable signal and a main word line enable signal. The low area driving unit(40) enables the decoder enable signal and main word line enable signal. The low area driving unit generates a sub word line enable signal and the main word line enable signal. The low area driving unit drives a cell array(50).