发明名称 SEMICONDUCTOR-DEVICE MANUFACTURING METHOD AND EXPOSURE METHOD
摘要 <p>PURPOSE: A semiconductor-device manufacturing method and an exposure method are provided to inspect an overlay error by considering the variation in a line-space pattern informing a sidewall. CONSTITUTION: A first layer(12) is formed to have a line portion and a space portion which are separated by a first pitch. The second level(14) is formed in the sidewall of the line portion of the first layer. The first layer is removed so that second layer includes a line portion and a space portion which are separated by a second pitch. A first pattern includes a line portion and a space portion which are separated by the second pitch. The displacement of the line portion of the first pattern is measured based on the width of the first and second portion.</p>
申请公布号 KR20100075405(A) 申请公布日期 2010.07.02
申请号 KR20090129727 申请日期 2009.12.23
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KOBAYASHI YUJI
分类号 H01L21/027 主分类号 H01L21/027
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