DELAY LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN ADDRESS STROBE WRITE LATENCY

摘要

PURPOSE: A delay locked loop circuit controlled by column address strobe write latency is provided to reduce current consumption by reducing the bias current of unit delays. CONSTITUTION: A delay line(21) comprises a plurality of unit delays. The delay line delays an external clock signal in response to a control signal. A phase detector(23) detects the phase difference between an output signal of the delay line and the external clock signal. A controller(25) generates a control signal. A control circuit controls the bias current of the unit delays according to column address strobe write latency.