发明名称 DISTRIBUTED MEMORY SYNCHRONIZED PROCESSING ARCHITECTURE
摘要 A data processing system comprises a plurality of processors, where each processor is coupled to a respective dedicated memory. The data processing system also comprises a voter module that is disposed between the plurality of processors and one or more peripheral devices such as a network interface, output device, input device, or the like. Each processor provides an I/O transaction to the voter module and the voter module determines whether a majority (or predominate) transaction is present among the I/O transactions received from each of the processors. If a majority transaction is present, the voter module releases the majority transaction to the peripheral. However, if no majority transaction is determined, the system outputs a no majority transaction signal (or raises an exception). Also, a processor error signal (or exception) is output for any processor providing an I/O transaction not corresponding to the majority transaction. The error signal may also optionaly prompt the recovery of any or all processors with methods such as but not limited to reboot/reset based upon predetermined or emergent criteria.
申请公布号 US2010169886(A1) 申请公布日期 2010.07.01
申请号 US20080347390 申请日期 2008.12.31
申请人 SEAKR ENGINEERING, INCORPORATED 发明人 TROXEL IAN;MURRAY PAUL
分类号 G06F9/46 主分类号 G06F9/46
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