发明名称 |
Ethernet System and Related Clock Synchronization Method |
摘要 |
A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.
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申请公布号 |
US2010169704(A1) |
申请公布日期 |
2010.07.01 |
申请号 |
US20090629897 |
申请日期 |
2009.12.03 |
申请人 |
YU TING-FA;HUANG LIANG-WEI;CHANG RONG-JEN;LI MING-JE |
发明人 |
YU TING-FA;HUANG LIANG-WEI;CHANG RONG-JEN;LI MING-JE |
分类号 |
G06F13/00;G06F1/12;G06F11/07 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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