PASSIVIERUNGSVERFAHREN FÜR EINE INTEGRIERTE SCHALTUNG

摘要

PCT No. PCT/US94/12780 Sec. 371 Date Jul. 13, 1995 Sec. 102(e) Date Jul. 13, 1995 PCT Filed Nov. 7, 1994 PCT Pub. No. WO96/14657 PCT Pub. Date May 17, 1996A method for forming a UV transmission passivation coating on an integrated circuit, such as EPROM, after completion of the active device and metal routing circuitry comprises depositing a first barrier dielectric layer over the integrated circuit; smoothing out underlying features by applying a layer of flowable dielectric over the first dielectric layer; and depositing a second dielectric layer over the flowable dielectric. Next a photoresist pattern is made over the second dielectric coating, having an opening layer over the at least one conductive pad. A wet etch process is used to remove portions of the second dielectric layer exposed by the opening. A dry etch process is used to remove portions of the remaining layers exposed through the opening, including the remaining portions of the second dielectric layer, the flowable dielectric layer and the first dielectric layer, down to the conductive pad. Finally, the photoresist is removed. The second dielectric layer is composed of a first protective dielectric, such as silicon oxynitride, deposited using plasma enhanced chemical vapor deposition, to protect the flowable dielectric layer from the subsequent wet etch process. The second dielectric layer also includes a top layer deposited using plasma enhanced chemical vapor deposition and comprising phosphorus doped silica to provide a stress buffer, and to prevent penetration of mobile ions to the first dielectric layer. The phosphorus doped silica layer is deposited using both high frequency and low frequency power for plasma formation during the deposition to increase the quality of the layer.