CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD

摘要

PURPOSE: A power converter of a co-packaging method based on a planar element, a structure thereof, and a manufacturing method thereof are provided to reduce power loss by integrating a schottky diode with a lower power MOSFET. CONSTITUTION: A voltage converter includes a semiconductor wafer unit and an output stage. An output stage includes an upper transistor and a lower transistor which are formed on a single die. The upper transistor includes an LDMOS(Lateral Diffusion Metal Oxide Semiconductor). The lower transistor includes a planar VDMOS(Vertical Diffusion Metal Oxide Semiconductor)(150). The voltage converter is co-packaged with a power die and includes a controller circuit on the electrically connected die.