发明名称 BUFFER CIRCUIT INSERTION METHOD, BUFFER CIRCUIT INSERTION DEVICE, AND BUFFER CIRCUIT INSERTION PROGRAM
摘要 PROBLEM TO BE SOLVED: To solve the problem that arrangement congestion on a layout pattern rises, and wiring property decreases in a conventional buffer circuit insertion method. SOLUTION: A buffer circuit insertion device includes: a storage part 11 for storing layout information and occupancy rate upper limit value; a buffer circuit insertion place retrieval part 10 for specifying an insertion place where a buffer circuit is inserted based on the layout information; a cell occupancy rate check part 12 for calculating the arrangement congestion of a prescribed region including the insertion place; and a buffer circuit insertion processing part 13 for arranging the buffer circuit in the prescribed region when the arrangement congestion is equal to or less than the occupancy rate upper limit value, and for outputting the layout information after the arrangement of the buffer circuit in the storage part. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010146047(A) 申请公布日期 2010.07.01
申请号 JP20080319156 申请日期 2008.12.16
申请人 RENESAS ELECTRONICS CORP 发明人 KITAYAMA TOMOHIRO
分类号 G06F17/50 主分类号 G06F17/50
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