发明名称 |
POWER EFFICIENT SYSTEM FOR RECOVERING AN ARCHITECTURE REGISTER MAPPING TABLE |
摘要 |
A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.
|
申请公布号 |
US2010169617(A1) |
申请公布日期 |
2010.07.01 |
申请号 |
US20090645767 |
申请日期 |
2009.12.23 |
申请人 |
STMICROELECTRONICS (BEIJING) R&D CO. LTD. |
发明人 |
SUN HONG-XIA;WANG KAI-FENG;ZHU PENG-FEI;WU YONG-QIANG CHRIS |
分类号 |
G06F9/00;G06F9/40 |
主分类号 |
G06F9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|