发明名称 |
Parametric Testline with Increased Test Pattern Areas |
摘要 |
An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
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申请公布号 |
US2010164521(A1) |
申请公布日期 |
2010.07.01 |
申请号 |
US20100704252 |
申请日期 |
2010.02.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN HSIEN-WEI;HSU SHIH-HSUN;TSAI HAO-YI;JENG SHIN-PUU |
分类号 |
G01R31/02 |
主分类号 |
G01R31/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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