| 摘要 |
An interface circuit for use in a baseband module, and receiving data from a radio frequency module intermittently, the data including a synchronization pattern followed by a payload data, the interface circuit includes: a receiver for receiving data transmitted from the radio frequency module; a timer for indicating estimated time intervals of intermittently transmitted data from the radio frequency module; and a processor for controlling detection of the synchronization pattern in portions of the received data included in a time window designated by the time intervals estimated by the timer, the processor validating detection of the synchronization pattern when at least a part of the data within the time window matches with a predetermined pattern and validating the payload data following the validated synchronization pattern. |
