发明名称 BIT LINE PRECHARGE CIRCUIT AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME
摘要 A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal.
申请公布号 US2010165768(A1) 申请公布日期 2010.07.01
申请号 US20090476349 申请日期 2009.06.02
申请人 WON HYUNG SIK 发明人 WON HYUNG SIK
分类号 G11C7/00 主分类号 G11C7/00
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