| 摘要 |
<p>A clock data recovery circuit that supports high and low data rates is provided. The circuit includes: a detection circuit (11) for detecting whether D1‰ D2 or D1‰ D3, assuming that logical values of an input data signal DATAIN sampled at timings t1, t2, and t3 (t2<t1<t3) of edges of clock signals CLK0 and CLK1 are D1, D2, and D3, respectively; and a clock generation circuit (14) for changing phases of the clock signals CLK0 and CLK1 based on detection results from the detection circuit (11), so that timings at which the logical values of the input data signal DATAIN change correspond to the timings t2 and t3.</p> |
