INTEGRATED CIRCUIT WITH INTEGRATED CAPACITOR

摘要

An explanation is given of, inter alia, a circuit arrangement in which an intermediate layer (160) made of a dielectric material is arranged between two metal layers (102 and 104). The intermediate layer (160) is designed in such a way that the capacitance per unit area between the connection layers (102, 104) is greater than 0.5 fF/μm2.