发明名称 TRANSLATING DEVICE, TRANSLATING METHOD AND TRANSLATING PROGRAM, AND PROCESSOR CORE CONTROL METHOD AND PROCESSOR
摘要 <p>When parallel processing is performed by a system configured by a plurality of processors and a multicore processor chip, power control code can be reduced by dynamically changing the number of processors for performing the parallel processing and an operation clock of each processor. A translation device includes: a parallel loop processing detection unit configured to detect from the source code a loop processing code for execution of an internal processing operation for a given number of repeating times, and an independent parallel loop processing code in the internal processing operation performed for each repetition to be concurrently processed; and a dynamic parallel conversion unit configured to generate a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code. The technology also relates to a translating method, a translating program, a control method for a processor core, and a processor.</p>
申请公布号 EP2202638(A1) 申请公布日期 2010.06.30
申请号 EP20070805864 申请日期 2007.09.21
申请人 FUJITSU LIMITED 发明人 YAMASHITA, KOICHIRO
分类号 G06F9/45;G06F1/04;G06F1/32;G06F9/50 主分类号 G06F9/45
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