Sample and hold circuit, multiplying D/A converter having the same, and A/D converter having the same

摘要

A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is α, a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is &bgr;, a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is γ, and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is &eegr;. α is substantially different from &bgr;. A total capacitance of a feedback capacitor pair is substantially equal to (α−&bgr;−γ+&eegr;)·(N/2), where N is a positive number.