发明名称 Chip scale package fabrication methods
摘要 Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.
申请公布号 US7745261(B2) 申请公布日期 2010.06.29
申请号 US20080109597 申请日期 2008.04.25
申请人 SHANGHAI KAIHONG TECHNOLOGY CO., LTD. 发明人 TAN XIAOCHUN;GUO JUN
分类号 H01L21/00 主分类号 H01L21/00
代理机构 代理人
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