| 摘要 |
Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.
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