| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a flip-chip structure for preventing deterioration in timing reliability due to an influence of stress applied from a pad to a chip internal element at low cost. <P>SOLUTION: A cell arrangement position of a pad lower side, or a pad arrangement position or a bump arrangement position, etc., which is influenced by stress is previously laid out such that an operation defect of an LSI due to the influence of the stress hardly occurs. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
