发明名称 |
CHIP STRUCTURE, CHIP LAMINATED STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE, AND MEMORY |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a chip structure avoiding warpage of a chip due to thickness reduction. <P>SOLUTION: The chip structure 1 includes a chip 3a and a chip 3b which are bonded together back to back. The chip 3a and the chip 3b have planar forms which are mutually mirror-reversed relative to bonded surfaces. Owing to this structure, warping stresses in the chip 3a and the chip 3b are canceled out, thereby, the entire warpage of the chip structure is avoided even with thickness reduction of the chip 3a and the chip 3b. <P>COPYRIGHT: (C)2010,JPO&INPIT |
申请公布号 |
JP2010140981(A) |
申请公布日期 |
2010.06.24 |
申请号 |
JP20080313909 |
申请日期 |
2008.12.10 |
申请人 |
ELPIDA MEMORY INC |
发明人 |
ABE SATOSHI;WASHITANI MOTOO |
分类号 |
H01L25/065;H01L25/07;H01L25/18 |
主分类号 |
H01L25/065 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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